Introduction

The I2C bus is simple to draw and easy to get wrong, because its reliability depends on the pull-ups, the capacitance, the addressing and the layout. NXP invented the bus and its interface ICs are the natural companion, so this application note explains the practical rules for a reliable I2C design with the NXP switch and expanders in a real product system.

The Bus Basics

The I2C bus uses two open-drain lines, SDA and SCL, with pull-up resistors, and every device on the bus can drive a line low but none drives it high, so the pull-up sets the high level and the rise time. The bus is addressed, so each device has an address, and the transfer is acknowledged, so the master can detect a missing device. The open-drain drive and the pull-ups are what make the bus shareable and what make the timing depend on the capacitance.

Speed Modes

The bus runs at the standard 100 kHz, the fast 400 kHz and the fast-plus 1 MHz modes, and the mode sets the pull-up and the capacitance budget. Choose the mode from the devices and the host, and confirm the timing at the worst-case temperature and voltage, because the rise time changes with the temperature and the pull-up tolerance.

Pull-ups and Capacitance

The pull-up value is a trade: a larger resistor gives a lower current but a slower rise, and a smaller resistor gives a faster rise but a higher current and a heavier load on the driver. Calculate the value from the bus voltage, the total capacitance and the mode, and keep the total capacitance within the limit, which is about 400 pF for the fast mode. Add a device and the capacitance grows, so plan the budget before the board is laid out.

Rise Time and the Temperature

The rise time is set by the pull-up and the capacitance, and it changes with the temperature, so check the timing at the cold and the hot corners. A bus that passes on the bench at room temperature can fail in the field if the margin is thin, so leave room in the budget.

The NXP Switch and Expanders

The NXP PCA9548A 8-channel switch fans the upstream pair out to eight downstream buses, so a designer can isolate a section, resolve an address conflict between identical devices, divide the capacitance and even translate the voltage between the two sides. The NXP PCA9555 and PCA9554 add sixteen or eight I/O ports over the same bus, with an interrupt to the host, so the I/O grows without a larger host. The address pins place several devices on one bus, so plan the map before the layout.

Addressing

Every device has a fixed base address plus the address pins, so several identical devices share a bus only if the pins give them different addresses. Where two devices have the same fixed address, use a switch to put them on separate channels, which is the clean way to resolve the conflict.

Layout and Signal Integrity

Keep the bus traces short and direct, place the pull-ups close to the master and the decoupling close to every device, and keep the bus away from the noisy switching nodes and the high-current paths. Use a ground plane, keep the capacitance within the limit and add a series resistor only where a long line rings. A tidy layout is what makes the bus reliable across the temperature range.

Hot-Plug and Isolation

Where a board is hot-plugged or a section can fault, a switch isolates it, so a fault does not take the whole bus down and the insertion does not disturb the running traffic. This is a practical reason to use the switch on a large or a modular system.

Verification

Validate the design on the bench by reading and writing every device on the bus, by measuring the rise time and the timing with a scope at the cold and the hot corners, and by exercising the switch under load. Our FAE team can review your calculations, your layout and your measurements and help you interpret them, so the bus performs in the product as it does on the bench.